Process-Induced Thermal Stress of Through Silicon Via and Its Releasing Structure Design
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摘要: 在3D SiP(三维系统级封装)的TSV(硅通孔)的工艺制造过程中,热应力会引发TSV周围的载流子迁移率的改变,进而改变3D系统级封装芯片的性能.针对这一问题,提出了一种TSV热应力释放槽结构,以期解决微机电系统(MEMS)应用的大尺寸TSV的热应力问题.在释放槽内外,硅衬底表面的应力得到有效隔离,表面应力大大降低.在结合可行工艺参数的基础上,通过数值模拟对比了3D与2D模型的区别、不同TSV材料的区别,计算应力释放槽的深度、位置、宽度等因素对硅衬底表面应力释放的效果,给出了TSV应力释放槽的布局建议.研究结果表明含有释放槽的TSV,释放槽外热应力可以减小至无释放槽情况下的40%~60%,保留区域的面积也相应降低.Abstract: In the process of through silicon via (TSV) for 3D system in package (3D SiP), thermal stress changes the mobility of carriers of silicon around TSV, and then influences the whole 3D SiP chip performance. Aimed at this problem, a new stress-releasing structure was proposed, named thermal-stress-releasing groove. Stress on the silicon substrate surface outside the groove can be isolated to a low level especially for large-sized TSV applications. Numerical simulation was used to obtain the relationship between the groove structure parameters and the resulting thermal stress distribution. Parameters including depth and width of the releasing groove and distance from the groove to the pad edge were also simulated to obtain the proportion of stress reduction. The numerical results show that, 40%~60% of the previous thermal stress could be reduced, so could keep-off-zone area, through the proposed stress-releasing groove design.
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